1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an improved word line driver circuit for a semiconductor memory device.
2. Discussion of the Related Art
Since word lines in early semiconductor memory devices were composed of polysilicon, which has a relatively high resistance, the time required for a decoding signal to be transmitted from a word line decoder to a memory cell, that is, the data access time, was very long.
A technique for solving the above problem was disclosed in the U.S. Pat. No. 4,542,486 and shown in FIG. 1, wherein a metal layer is formed on each word line. Referring to FIG. 1, a memory cell array 1 is divided into a plurality of blocks (1A, 1B, 1C). Each word line is divided into a main word line 15 and sub word lines 3A, 3B, 3C composed of metal material and having an AND gate with a small resistance and a small parasitic capacitance. Only a word line in a specific block is made to be operated in accordance with a cell block select signal.
The operation of the above word line structure will now be described. First, when one of the column decoders (not illustrated) arranged in the y-direction is enabled in accordance with a column address signal, a corresponding main word line becomes high to be active. Then, a specific block is selected by an address in the x-direction, and a block select signal also becomes high. As a result, one of the AND gates 16A, 16B, 16C is turned on to enable a corresponding sub word line, thus completing the operation.
The above-described construction works well in a semiconductor memory device having a small capacity. However, for a device having 64 mega bits or greater capacity, when a metal layer is formed on each word line, the chip area is accordingly increased. This makes practical application of this construction to semiconductor memory devices almost impossible. Furthermore, since the block select signal is used as a gate input signal and is simultaneously inputted to a plurality of AND gates, the load capacity of the block select signal is increased and the enabling speed of the sub word lines becomes slower, resulting in the increased power consumption due to the large load capacity.
Accordingly, as shown in FIG. 2, in a 64 mega bits or greater level device, to improve the enabling speed of the sub word lines in the arrangements of FIG. 1, one metal layer is allocated to a plurality of word lines having a hierarchial structure. In addition, a driving unit is disposed to selectively connect the word lines and the metal layer.
The semiconductor memory device structure shown in FIG. 2 is disclosed in the U.S. Pat. No. 5,416,748, in which one metal layer is connected to a plurality of word lines. The device structure includes a plurality of main word lines (MWL-1, . . . , MWL-n) composed of a metal material, and a plurality of sub word lines (SWL) connected to one main word line. A column decoder 10 generates a column address. Sub word line driving units (SWD) 20 select a specific sub word line among the plurality of sub word lines. A sense amplifier 30 amplifies a signal of the selected word line. A block decoder (BD) 40 outputs a block select signal. Word line drive decoders (WDD) 50 drive the word lines, and sub decoding drive units (SDD) 60 select one of the word line drive decoders (WDD) 50.
As shown in FIG. 3, each word line drive decoder (WDD) 50 includes NAND gates 51 and 511 each receiving a block select signal (AI1) and the respective main word line decoding signals AI2 and AI3. Inverters 52 and 521 respectively invert the output signal from the NAND gates 51 and 511. A level shifter including PMOS and NMOS transistors converts an inputted voltage (V).
The operation of the semiconductor memory device having the above-described word line drive unit will now be described. The column address enables the column decoder 10 located in the y-direction to make one main word line high to be active, and this main word line then transmits the resultant high active main word line signal to all of the sub word line drive units (SWD) connected thereto. Then, the column address is inputted to the sub decoding drive units (SDD) disposed in the x-direction which make one of the decoding signals of one column high to be active.
The resultant high active decoding signal is transmitted to the word line drive decoder (WDD) of that column as shown in FIG. 3 to drive a selected block, together with a decoding signal from the block decoder 40 enabled by the column address.
In the active word line drive decoder (WDD), the decoding signal is made to be a sub decoding signal for applying power to a sub power node of the sub word line drive unit (SWD) in the selected block. The sub word line drive unit (SWD) located where the high active main word line and the sub decoding signal cross is made active to drive a sub word line.
However, according to the word line drive decoder structure shown in FIG. 3, the block select signal and the sub decoding signal are inputted to the NAND gates, and a plurality of sub word line driving units are simultaneously enabled, resulting in the increased power consumption. Since a sub decoding drive unit is provided in each block, an overlapping power consumption results. Moreover, since a word line drive decoder including the NAND gate, the inverter and a level shifter, and a sub decoding drive unit must be provided in each block, the layout area in fabricating a chip is increased.